This invention relates to a phase locked loop circuit using a Schmitt trigger where in response to a VCO input control voltage adjusts an aspect ratio of pump UP transistors to that of pump DOWN transistors in a charge pump circuit block to achieve a very small steady state phase error at an input of a phase comparator block
Phase locked loop circuits are very important building blocks in data transmission systems. They are used in many different applications for example to eliminate skew between communicating chips, to recover a clock signal from random input data, or to frequency multiply a low frequency signal to a high frequency one.
Various phase locked loop circuits of the type are already known. One example is an article which is contributed by Hiromi Notani et al. to 1994 Symposium on VLSI Circuits Digest of Technical Papers, pages 129-130, under the title of "A 622-MHz CMOS Phase-Locked Loop with Precharge-type Phase Frequency Detector." Another example is disclosed in U.S. Pat. No. 5,576,647 issued to Sutardja et al. under the title of the invention "CHARGE PUMP FOR PHASE LOCKED LOOP. "
In the manner which will later be described in conjunction with FIG. 1, a conventional phase locked loop circuit comprises a phase comparator block, a charge pump block, a low-pass filter (LPF) block, a voltage controlled oscillator (VCO), a frequency divider, a reference input terminal, and a timing (clock signal) output terminal.
The phase comparator block compares an input reference signal having a reference frequency to a feedback signal having a divided frequency. A phase difference between the input reference signal and the feedback signal determines phase compared outputs of the phase comparator block. When the phase of the feedback signal leads the phase of the input reference signal, the phase comparator block generates a pulse train of negative pulses as a pump-down signal. The width of those pulses equals the phase difference between the input reference signal and the feedback signal. Conversely when the phase of the feedback signal lags that of the input reference signal, the phase comparator block produces a pulse train of negative pulses as a pump-up signal. The width of these pulses equals the phase difference between the input reference signal and the feedback signal. When there is no phase difference between the input reference signal and the feedback signal, no pulse output is produced.
The phase compared outputs are subsequently supplied to the charge pump block. Depending on the phase compared outputs DN and UP, the charge pump block functions to either charge or discharge an input node of the low-pass filter block. The low-pass filter block is charged when the pump-up signal is low and the pump-down signal is high. Conversely, the low-pass filter block is discharged when the pump-up signal is high and the pump-down signal is low. When both the pump-up signal and the pump-down signal are high, the charge pump block is disabled in which case the low-pass filter block is neither charged nor discharged. In this case, the low-pass filter block is isolated from the charge pump block and the phase comparator block.
Therefore, the charge pump block is basically a tri-state (charging, discharging or open) switch. A charge pump output signal of the charge pump block is converted to a DC (direct current) voltage or a control voltage by means of the low-pass filter block. The low-pass filter block determines the response characteristics of the PLL circuit i.e. a natural frequency .omega..sub.n and a damping factor .zeta..
The VCO is supplied with the control voltage and produces an output clock signal (a VCO output signal) having a VCO frequency. The VCO consists of a bias generator and a current controlled oscillator. The VCO output signal varies in a range about multiple of the reference frequency in response to the control voltage. The output clock signal is then frequency divided down by the frequency divider to produce a divided clock signal as the feedback signal having the feedback frequency. Negative feedback operation of the PLL circuit results in the phase difference between the input reference signal and the feedback signal becoming a minimum, the so-called `phase locked state`.
In the manner which will later be described in conjunction with FIG. 3, a conventional charge pump block comprises a PMOS pump UP transistor and an NNOS pump DOWN transistor. The PMOS pump UP transistor has a source connected to VDD while the NMOS pump DOWN transistor has a source connected to GND. Both of the transistors have drains which are connected together to produce the charge pump output signal. A first inverter provides a necessary inversion of the pump-down signal to produce an inverted pump-down signal DNBAR which drives the gate of the NMOS pump DOWN transistor. Second and third inverters buffer the pump-up signal to produce a buffered pump-up signal which drives the gate of the PMOS pump UP transistor.
When the pump-up and the pump-down signals from the phase comparator block are low and high, respectively, the PMOS pump UP transistor turns ON and delivers a pump UP current as the charge pump output signal. Similarly, when the pump-up signal and the pump-down signal from the phase comparator block are high and low, respectively, the NMOS pump DOWN transistor turns ON and delivers a pump DOWN current as the charge pump output signal.
In the ideal phase-locked condition, there would be no phase difference between the input reference signal and the feedback signal. Hence, both of the pump-up and the pump-down signals would remain high, thereby isolating the input node of the low-pass filter block from the phase comparator block. However, in reality, finite PLL loop gain results in some phase difference always existing between the input reference signal and the feedback signal. This erroneous phase difference causes the charge pump block to either produce a corrective pump-up signal or a corrective pump-down signal. While this is the case, the average pump up current flowing in the PMOS pump UP transistor equals the average pump down current flowing in the NMOS pump DOWN transistor. In order to satisfy this condition, the transistors are ratioed proportionally at Vcp=VDD/2.
In the manner which will later be described in conjunction with FIG. 4, the average pump up current and the average pump down current vary as a function of the PLL lock voltage (the charge pump output signal). While the average pump up current is equal to the average pump down current for the PLL lock voltage which is approximately equal to half of VDD, the bigger the mismatch between the average pump up current and the average pump down current becomes as the PLL lock voltage moves towards either VDD or GND. The bigger the mismatch in currents, the bigger the phase error offset (or steady state phase error as it's called) required as the input of the phase comparator to satisfy the condition of the average pump up current equal to the average pump down current at phase lock, The range of the PLL lock voltage depends on the process condition of the chip at the time of manufacture and VCO design. While conventional NMOS input VCOs have a relatively limited lock voltage range, recently proposed complementary type VCOs (both NMOS input and PMOS input) have a much wider lock voltage range. Hence, conventional charge pump circuits used with these type of VCOs would produce even larger steady state phase errors.
Large steady state phase errors cause for example an increase in error bit rate in a clock recovery circuit or increase the skew between two communicating chips. Furthermore, since most lock detectors use phase differences to detect the locked state, this steady state phase error can cause an erroneous lock detection to occur.
Thus in summary, a phase locked loop circuit is needed which achieves a very small steady state phase error for all values of PLL lock voltage.